1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory using a burn-in method.
2. Related Art
Failures in semiconductor memories such as static random access memories (SRAM)s are classified into initial failures, accidental failures and wear failures. The initial failures are those that are caused by defects and deficiencies. The accidental failures are determined by the reliability characteristic to the semiconductor memories and the wear failures are caused by the service life of the semiconductor memories.
A burn-in step is conducted to remove the initial failures among these failures. The burn-in is a test that gives accelerated stresses on semiconductor memories by operating the semiconductor memories with temperatures and voltages that are higher than the normal operating conditions, to thereby remove in a short time defective products having initial failures. The initial failures occur at a higher rate than those of the other failures. Accordingly, by removing semiconductor memories that may have initial failures by the burn-in step, the reliability of semiconductor memories is improved.
Conventionally, the burn-in step is conducted after the semiconductor memory has been assembled into a final shipping configuration such as a molded package, which would waste the assembly costs for chips that are found defective by the burn-in test. As such, there are high demands in conducting the burn-in step when the semiconductor memory is in its wafer state.
In a normal wafer-level burn-in stop, probe needles are brought in contact with address terminals, data input (input/output) terminals and control terminals of semiconductor memories, and a voltage stress is applied to each of the memory cells. In this step, a special burn-in apparatus is often used such that the operation is conducted under a temperature condition higher than an operation temperature range specified by the semiconductor memory, and the stresses can be simultaneously applied to many chips in one probe contact. In this case, since the probes for the burn-in test are provided in addition to the probes for the normal wafer test, the frequency in which the probe needles are brought in contact with the respective terminals increases, which damages the terminals, and results in a lower yield.
It is an advantage of the present invention to provide semiconductor memories and a burn-in method for the same, which prevents the yield from lowering due to damages on address terminals and data input (input/output) terminals caused by probe needles particularly in a wafer-level burn-in test, and shortens the time required for the burn-in test.
In accordance with one embodiment of present invention, a semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inputting a burn-in mode signal burn-in mode signal to place the semiconductor memory in a burn-in mode and a fourth terminal for inputting an external clock signals. The semiconductor memory further includes an address signal generation section that generates an address signal for selecting each of the plurality of memory cells based on counting of the clock signal while the burn-in mode signal is input. A data signal generation section generates a data signal based on the clock signal while the burn-in mode signal is input. A data writing section writes data of the data signal in the memory cells selected by the address signal.
In accordance with the embodiment of the present invention, an address signal for selecting each of the plurality of memory cells is generated based on the counting of an external clock signal, a data signal is generated based on the external clock signal, and data are written in the memory cells. Therefore, the burn-in test does not require address terminals, data input (input/output) terminals, and control terminals that are used for the normal operation, such that the address terminals, data input (input/output) terminals, control terminals can be prevented from damages. Accordingly, the embodiment of the present invention can improve the yield in manufacturing semiconductor memories.
Also, in accordance with the embodiment of the present invention, terminals used for burn-in are only the first through fourth terminals, which makes it possible to increase the number of chips that can be burnt in at once, in view of the fact that the number of terminals of a burn-in apparatus is limited. As a result, the burn-in time for each wafer can be shortened.
Also, in accordance with the embodiment of the present invention, an address signal for selecting each of the plurality of memory cells is generated based on the counting of the clock signal, in other words, addresses are generated in series, which makes it unnecessary to use a complex address signal generation circuit.
Examples of the address signal generation section, the display signal generation section, and the data writing section are described below in the section Burn-in Mode illustrating embodiments of the present invention. It is noted that the power supply terminal is, for example, a VDD terminal, and the ground terminal is, for example, a VSS terminal.
In accordance with another embodiment of the present invention, the first terminal, the second terminal, the third terminal and the fourth terminal may be exclusively used for the burn-in mode, and the embodiment may further include a fifth terminal that is different from the first terminal and becomes a power supply terminal for the semiconductor memory, and a sixth terminal that is different from the second terminal and becomes a ground terminal for the semiconductor memory.
In the structure described above, since the first terminal, the second terminal, the third terminal and the fourth terminal may be exclusively used for burn-in, the use of the semiconductor memory is not affected even when these terminals are damaged due to contacts of the probe needles in a burn-in test.
In accordance with the above embodiment of the present invention, the address signal generation section may include a counter, wherein an output from the counter may be used as the address signal.
In accordance with another embodiment of the present invention, the data signal generation section may be equipped with a signal divider that divides an output signal from a flip-flop at the last stage of the counter, and may generate the data signal based on a signal output from the signal divider.
By so doing, a first level is written in the plurality of memory cells first and then a second level can be written therein. Accordingly, a stress at the first level and a stress at the second level can be applied to each of the memory cells, which makes it possible to apply efficient stresses to each of the memory cells. For the first level and the second level, the following two cases may apply. For example, the first level is a H level, and the second level is a L level. Conversely, the first level is a L level, and the second level is a H level. It is noted that an example of the signal divider will be described below in the section Burn-in Mode illustrating embodiments of the present invention.
The embodiment of the present invention may further be equipped with a device that releases a function to terminate a selection period for a word line and a bit line pair earlier than a cycle time, based on the burn-in mode signal.
By so doing, the selected memory cells can be placed under stresses for a longer time compared to the case where they are normally operated. As a result, the time for burn-in can be shortened. It is noted that the function to terminate the selection period for a word line and a bit line pair earlier than the cycle time is one of the functions to lower the power consumption, for example, an automatic power-down function. One example of this device is described below in the section Release of Automatic Power-down illustrating embodiments of the present invention.
The embodiment of the present invention may be further equipped with an address signal input circuit at which an external address signal is input, and a data signal input circuit at which an external data signal is input. The address signal input circuit may prohibit input of the external address signal by the burn-in mode signal, and the data signal input circuit may prohibit input of the external data signal by the burn-in mode signal.
By the structure described above, the burn-in is conducted while inputs of the address signal and data signal from outside are prohibited. As a result, even when the input terminals are open, a through current is prevented from flowing through the input circuit.
In accordance with another embodiment of the present invention a burn-in method for a semiconductor memory having a plurality of memory calls includes placing the semiconductor memory in a burn-in mode, supplying a potential to the semiconductor memory, generating an address for each of the plurality of memory cells based on counting of an external clock signal during the burn-in mode, generating data based on the clock signal during the burn-in mode, and writing the data in the memory cells corresponding to the addresses.
In accordance with the other embodiments of the present invention, a semiconductor memory practices the steps recited above.
In accordance with the other embodiments of the present invention, the writing data may be conducted while releasing a function to terminate a selection period for a word line and a bit line pair earlier than a cycle time.
As a result, the present invention may further be equipped with a device that releases a function to terminate a selection period for a word line and a bit line pair earlier than a cycle time, based on the burn-in mode signal.
In accordance with the other embodiments of the present invention, the writing of data writes a first level in the plurality of memory cells, and then writes a second level therein.
As a result, the data signal generation section may be equipped with a signal divider that divides an output signal from a flip-flop at the last stage of the counter, and may generate the data signal based on a signal output from the signal divider
The other embodiments of the present invention prohibit input of external address and data during the burn-in mode.
As a result, the present invention may be further equipped with an address signal input circuit at which an external address signal is input, and a data signal input circuit at which an external data signal is input. The address signal input circuit may prohibit input of the external address signal by the burn-in mode signal, and the data signal input circuit may prohibit input of the external data signal by the burn-in mode signal.
In accordance with the other embodiments of the present invention, the burn-in may be conducted at a wafer-level.
Since the number of terminals that are brought in contact with probe needles in a burn-in step can be reduced, the number of chips that can be subject to a burn-in step at once can be increased, when the burn-in is conducted at a wafer-level.